特許の英語（特許翻訳分野）

先端プロセス

先端プロセス
leading process

7074714
Therefore, the leading process for formation of copper-comprising devices is a damascene structure, which requires the filling of embedded trenches and/or vias.

ダブルパターニング

ダブルパターニング
double patterning

7064078
In the double patterning method, a hardmask layer is deposited on a substrate layer that is to be etched. The hardmask layer is patterned by a photoresist deposited on the hardmask layer. The photoresist is then removed, and a second pattern is introduced into the hardmask layer with a second photoresist that is deposited on the hardmask layer.

ARC

ARC
Antireflective Coating（反射防止膜）

6291356
Silicon oxynitride is primarily used as an antireflective coating (ARC) and is often referred to as a "dielectric ARC".

電子ビーム検査

電子ビーム検査
electron beam inspection

7183546
During electron beam inspection of the SOI wafer each of the epilayer islands 230, 232 and 234 acts like a capacitor and is charged to a certain voltage level.

EBL

EBL
Electron Beam Lithography（電子ビームリソグラフィ）

6724002
An electron beam lithography system includes a laser for generating a laser beam, and a beam splitter for splitting the laser beam into a plurality of light beams.

窒化物

窒化物
nitride

6362109
A multi-step process is possible in which the different oxide and nitride levels are sequentially etched.

コンタクトプラグ

コンタクトプラグ
contact plug

6750156
In electronic circuit fabrication, an interconnect feature, such as a wiring line or a contact plug, is used to electrically connect electronic features that are formed on a substrate.

シンニング

シンニング
thinning

6677239
Silicon nitride loss may take the form of excess removal of silicon nitride, or "thinning" of the silicon nitride layer, from the desired amount 60 of silicon nitride.

エロージョン

エロージョン
erosion

6656842
As used throughout this disclosure, the term, "erosion" denotes the height differential between the oxide in the open field and the height of the oxide within the dense array.

ディッシング

ディッシング
dishing

6656842
As also used throughout this disclosure, the term "dishing" denotes a difference in height between the oxide and Cu within the dense array.

スラリ

スラリ
slurry

6280299
A slurry is delivered to the center of the polishing pad to chemically passivate or oxidize the film being polished and abrasively remove or polish off the surface of the film.

結晶方位

結晶方位
crystal orientation

6991999
The method of forming an electrode comprising: forming a lower polysilicon film having a crystal orientation dominated by the <111> direction;

格子定数

格子定数
lattice constant

6770134
The lattice constant of Ge is 4% larger than that of Si.

ALE

ALE
atomic layer epitaxy（原子層エピタキシ）

7078302
Dielectric layer 20 may be deposited to substrate 10 by a variety of deposition processes, such as rapid thermal oxidation (RTO), chemical vapor deposition (CVD), plasma enhanced-CVD (PE-CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), atomic layer epitaxy (ALE) or combinations thereof.

イオンプレーティング

イオンプレーティング
ion plating

6277253
Ion plating and CVD may be considered vacuum processes because they are generally carried out in a vacuum chamber.

ECR

ECR
electron cyclotron resonance

6518206
The source of the high density plasma may be any suitable high density source, such as electron cyclotron resonance (ECR), helicon resonance or inductively coupled plasma (ICP)-type sources.

スカベンジャー

スカベンジャー
scavenger

6455232
In accordance with the invention, the scavenger reacts with the free fluorine generated by the dissociation of fluorine-containing polymer during the resist strip step and reduces the content of free fluorine in the plasma.

TMAH

TMAH
tetramethyl ammonium hydroxide
（水酸化テトラメチルアンモニウム）

半導体の製造工程において使用される現像液のひとつを指す。

6605394
This developer is a 2.38 wt % solution of tetramethyl ammonium hydroxide (TMAH).

RET

RET
Resolution Enhancement Techniques（超解像技術）

6268093
Another method for increasing the resolution of the image is the use of RET (Resolution Enhancement Techniques) which include: off axis illumination, OPC (Optical Proximity Correction) reticles, and PSM (Phase Shift Mask) reticles.

２層

２層
bilayer

6245653
A method as recited in claim 3, wherein said barrier layer is selected from the group consisting of a TiN layer, a bilayer of Ti and TiN and a trilayer of Ti/TiN/TiN, wherein x is less than 1.

高アスペクト比

高アスペクト比
high-aspect-ratio

6136685
Narrow, high-aspect-ratio gaps are difficult to fill in prior art CVD processes because the CVD material, accumulating on the corners of adjacent features as overhangs, often closes the gap from both sides before the gap is filled.

---------

半導体製造でのアスペクト比は、エッチングなどでウェーハ上に形成されたパターンの深さと幅の比。アスペクト比＝深さ/幅で表され、高アスペクト比は、この値が大きいことであり、加工・計測などが難しくなる。
(SEAJより引用)

AFM

AFM
Atomic Force Microscope（原子間力顕微鏡）

5925225
The term "AFM" (Atomic Force Microscope) refers to a technique commonly used to measure film surface roughness, wherein a microprobe in contact with the film surface is drawn across the film and the mechanical movement of the microprobe is translated to a digital signal which is plotted out.

CD-SEM

CD-SEM
Critical Dimension Scanning Electron Microscope（測長走査型電子顕微鏡）

6897442
Charged particle beam columns are typically employed in scanning electron microscopy (SEM), which is a known technique widely used in the manufacture of semiconductor devices, being utilized in CD metrology tools, the so-called CD-SEM (Critical Dimension Scanning Electron Microscope) and defect review SEM (DR-SEM).

サセプタ

サセプタ
susceptor

4081313
In the preferred embodiments, a susceptor is utilized to support the substrates in the reaction chamber.

IMD

IMD
intermetal dielectric（メタル間絶縁体、金属配線層間絶縁体）

6465372
Low dielectric constant films are particularly desirable for premetal dielectric (PMD) layers and intermetal dielectric (IMD) layers to reduce the RC time delay of the interconnect metallization, to prevent cross-talk between the different levels of metallization, and to reduce device power consumption.

浮遊容量

浮遊容量
stray capacitance

6414648
Instabilities arise particularly where the coil inductance is sufficiently great so that, in combination with stray capacitance, self-resonance occurs near the frequency of the RF signal applied to the coil.

SOI

SOI
Silicon On Insulator

6489241
FIG. 5 is an illustration of a cluster tool which can be used to form a silicon on insulator (SOI) substrate in accordance with an implant and cleave process in accordance with the present invention.

薄膜形成

薄膜形成
thin film deposition

5419029
In thin film deposition and etch processes, such as physical vapor deposition ("PVD"), or "sputtering," a target material is bombarded by high energy gaseous ions.
***
6080665
PVD techniques for thin film deposition may be preferable because the resulting film is typically higher in purity than other films and PVD techniques are less costly.
***
6605319
After a thin film deposition step, an annealing step is performed by Rapid Thermal Processing ("RTP").

RTA処理

RTA処理
RTA processing

6551488
RTA processing typically requires a temperature increase of at least 50.degree. C. per second.

RTA

RTA
rapid thermal annealing

6280183
Rapid thermal processing (RTP), for example, is used for several different fabrication processes, including rapid thermal annealing (RTA), rapid thermal cleaning (RTC), rapid thermal chemical vapor deposition (RTCVD), rapid thermal oxidation (RTO), rapid thermal nitridation (RTN), and rapid thermal silicidation (RTS).

ウェットエッチング

ウェットエッチング
wet etching

5545289
After wet etching, the wafer was rinsed in deionized water to remove residual wet etchant.
***
6245684
wet etching the layer of silicon dioxide by immersing the film stack in a wet etch solution comprising an oxygen-selective liquid reagent for a period of time sufficient to form an undercut beneath the silicon nitride layer
***
5786276
In the past, silicon nitride was selectively removed by way of wet etching with hot phosphoric acid (e.g., 160.degree. C.). Wet etching suffers from drawbacks such as: difficulty of filtering out unwanted particles from the viscous etch liquid;

ペリクル

ペリクル
pellicle

6394109
In general, a pellicle is a transparent membrane that seals the mask (also referred to as a reticle) from harmful particle contamination. The pellicle is designed to be placed directly onto the mask to prevent particulates and other contaminants from falling onto the surface of the mask.

shear stress

shear stress
せん断応力

6570137
Sagging occurs as the filaments plastically deform in response to an applied shear stress, such as gravity.

tensile stress

tensile stress
引張応力

7091137
The stress test includes depositing a layer of material to be examined on top of a layer of TEOS oxide which has a high tensile stress and then subjecting the stack to 85.degree. C. and 85% humidity for 17 hours.

compressive stress

compressive stress
圧縮応力

4854263
That is, increasing the frequency tends to increase tensile stress (or decrease compressive stress); increasing power has the opposite effect; and varying the electrode spacing has the same tendency as does varying the frequency, but the effect is smaller.

ロングスロースパッタリング

ロングスロースパッタリング
long throw sputtering

5985759
Long throw sputtering enables control of the degree of directionality in the deposition of film layers, resulting in the deposition of thin, conformal coatings on sidewalls of a trench.

DCスパッタ

DCスパッタ
DC sputtering

6837975
In DC sputtering, a negative voltage is applied to the target sufficient to discharge the argon into a plasma.

ロードロック

ロードロック
load lock

5958510
Thus, after the deposition, the substrate may be removed from the deposition chamber, placed in a storage area in the load lock chamber between processing chambers, and allowed to reach ambient temperature.
***
5958510
Alternatively, the substrate may be moved from the load lock chamber to other chambers for subsequent processing without removing the substrate from the vacuum environment, e.g., moved to another chamber for PECVD formation of a silicon dioxide (SiO.sub.2) film thereon.
***
5958510
Such a vacuum processing chamber is available from Applied Materials, Inc., such as an oxide etch chamber, which may be connected, via a load lock mechanism to other vacuum or closed chambers in a semiconductor substrate processing apparatus, such as the multi-chambered 5000 Series processing apparatus available from Applied Materials, Inc., without exposing the substrate to the atmosphere.

TFT

TFT
thin film transistor（薄膜トランジスタ）

5441768
More recently, thin film transistors (TFT) have been used to separately address areas of the liquid crystal cell at very fast rates.

熱窒化

熱窒化
thermal nitridation

6387761
For example, silicon nitride film 205 can be formed by thermal nitridation by placing substrate 200 into a low pressure chemical vapor deposition (LPCVD) furnace and heating substrate 200 to a temperature between 800-950.degree. C.

レジスト剥離

レジスト剥離
resist stripping

6817377
Applied Materials
Resist stripping processes use O.sub.2 and other gases to strip resist from the substrate.
***
6479884
IBM
By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material.
***
4508757
IBM
The resist layer 28 is then removed from the surface using an appropriate resist stripping solution such as sulfuric/nitric acid or oxygen ashing in a plasma reactor.

エッチング

エッチング
etching

6368978
Etching is performed at a substrate temperature of 100.degree. C. or lower.
***
5298465
Etching is performed in a housing for processing a semiconductor wafer having a wafer perimeter defined by an outer wafer edge, a top surface and a bottom surface.
***
6014979
This type of etching is desirable for forming features such as tapered vias for multilayer metal containing contact structures used to electrically connect two or more electrically conductive layers separated by an insulating dielectric layer.
***
5354417
A resist material 26, such as photoresist or oxide hardmask, which is substantially resistant to etching is applied on top of the substrate layers 24.
***
6308654
Etching is required that is highly anisotropic and very highly selective for silica over silicon.
***
6551941
When the silicon-containing gate layer is polysilicon or amorphous silicon, etching is typically performed using a plasma generated from a source gas which comprises at least one etchant gas selected from the group consisting of a fluorine-comprising gas, a chlorine-comprising gas, and a bromine-comprising gas.
***
6551941
During this step, etching is performed using a plasma generated from a source gas which provides excellent (at least 20:1) selectivity for etching the silicon-containing gate layer relative to the gate dielectric layer, to avoid breaking through the thin gate dielectric layer. (The term "selectivity" is typically used to refer to a ratio of etch rates of two materials.)
***
5851926
The pressure during etching is generally maintained at about 20 to 25 millitorr to maintain straight sidewalls of the etched profiles.
***
6703315
In preferred embodiments of the present invention, etching is carried out in a DPS (decoupled plasma source) etching system.
***
6547977
In particular, the etching is carried out using an oxygen plasma etch with a small amount of CF.sub.4 present.
***
6325861
Etching is typically performed using a capacitively or inductively coupled plasma of halogen-containing gases, as for example described in Silicon Processing for the VLSI Era, Vol. 1, Chapter 16, by Wolf and Tauber, Lattice Press, 1986, which is incorporated herein by reference.
***
6211092
The dual-damascene process is particularly useful for copper metallization because no copper etching is required.
***
6087265
The plasma etching is conducted for producing semiconductor integrated circuits containing platinum electrodes.

成膜プロセス

成膜プロセス
deposition process

5807785
One of the primary steps in the fabrication of modern semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition or CVD.
***
6194038
Many different techniques have been implemented to improve the gap-filling characteristics of dielectric layers, including deposition etch-back (dep-etch) techniques. One such dep-etch technique involves physical sputtering of the dielectric layer by ion bombardment to prevent the formation of voids during a deposition process.
***
6020035
During a deposition process, the plasma heats the entire process chamber 10, including the walls of the chamber body 15a surrounding the exhaust passageway 23 and the shutoff valve 24.

レチクル

レチクル
reticle

7067227
A reticle is typically a thin layer of a metal-containing layer (such as a chrome-containing, molybdenum-containing, or tungsten-containing material, for example) deposited on a glass or quartz plate.
***
6960413
Photolithographic reticles typically include a substrate made of an optically transparent material, such as quartz or fused silica (i.e., silicon dioxide, SiO.sub.2), having an opaque light-shielding layer of metal, or photomask, typically chromium, deposited on the surface of the substrate.
***
7115517
During the patterning process, the photoresist layer 212 is exposed through a patterned reticle, developed, and then the undeveloped portion of the photoresist layer is removed.
***
6603873
One important process requiring careful inspection is photolithography, wherein masks or "reticles", are used to transfer circuitry features to semiconductor wafers.

リソグラフィ、レチクルの説明文 02

レチクルについては、以下の明細書などが分かりやすい。

6703169
Applied Materials, Inc.

FIELD OF THE INVENTION

In general, the present invention relates to a method of producing a lithographic mask (reticle) for use in the semiconductor industry. In particular, the invention pertains to a particular combination of process steps useful in preparing optically imaged high performance photomasks. The optical imaging of the photomask makes use of a deep ultraviolet (DUV) photoresist in combination with at least one antireflective coating (ARC). The DUV photoresist is imaged using an optical direct write continuous laser mask writing tool.

BRIEF DESCRIPTION OF THE BACKGROUND ART

Photoresist compositions are used in microlithographic processes for making miniaturized electronic components, such as in the fabrication of semiconductor device structures. The miniaturized electronic device structure patterns are typically created by transferring a pattern from a patterned masking layer overlying the semiconductor substrate rather than by direct write on the semiconductor substrate, because of the time economy which can be achieved by blanket processing through a patterned masking layer. With regard to semiconductor device processing, the patterned masking layer may be a patterned photoresist layer or may be a patterned "hard" masking layer (typically an inorganic material or a high temperature organic material) which resides on the surface of the semiconductor device structure to be patterned. The patterned masking layer is typically created using another mask which is frequently referred to as a photomask or reticle. A reticle is typically a thin layer of a metal-containing layer (such as a chrome-containing, molybdenum-containing, or tungsten-containing material, for example) deposited on a glass or quartz plate. The reticle is patterned to contain a "hard copy" of the individual device structure pattern to be recreated on the masking layer overlying a semiconductor structure.

A reticle may be created by a number of different techniques, depending on the method of writing the pattern on the reticle. Due to the dimensional requirements of today's semiconductor structures, the writing method is generally with a laser or e-beam. A typical process for forming a reticle may include: providing a glass or quartz plate, depositing a chrome-containing layer on the glass or quartz surface, depositing an antireflective coating (ARC) over the chrome-containing layer, applying a photoresist layer over the ARC layer, direct writing on the photoresist layer to form a desired pattern, developing the pattern in the photoresist layer, etching the pattern into the chrome layer, and removing the residual photoresist layer. When the area of the photoresist layer contacted by the writing radiation becomes easier to remove during development, the photoresist is referred to as a positive-working photoresist. When the area of the photoresist layer contacted by the writing radiation becomes more difficult to remove during development, the photoresist is referred to as a negative-working photoresist. Advanced reticle manufacturing materials frequently include combinations of layers of materials selected from chromium, chromium oxide, chromium oxynitride, molybdenum, molybdenum silicide, and molybdenum tungsten silicide, for example.

リソグラフィ、レチクルの説明文

レチクルについては、以下の明細書などが分かりやすい。

6251217
Applied Materials, Inc.

1. Field of the Invention

The invention generally relates to reactive ion etching systems for photomask fabrication upon a reticle and, more particularly, to a reticle adapter that facilitates dry etching a photomask using a conventional reactive ion etch chamber.

2. Background of the Invention

Semiconductor lithography is accomplished using a reticle comprising a relatively thick substrate typically fabricated of quartz, having a photomask fabricated of chrome patterned upon the surface of the substrate. A reticle is generally 5 inches by 5 inches, 6 inches by 6 inches or 9 inches by 9 inches. To fabricate the photomask pattern, a uniform submicron (e.g., 0.1 to 1.0 micron) thick layer of chrome has a photoresist layer applied thereto. The photoresist is then patterned using conventional laser or electron beam patterning equipment. The chrome layer is then etched using a wet etch process to remove material not protected by the photoresist. The isotropic characteristic of a wet etch causes an undercut phenomenon to occur below the photoresist material such that the chrome lines that are patterned upon the reticle are not uniformly spaced nor do they have vertical side walls. Such undercut on photomask patterns that will be used to produce sub 0.25 .mu.m devices can result in erroneous lithography.

露光

露光
exposure

5968324
The exposure wavelengths used in these laser lithographies are 365 nm, 248 nm, and 193 nm, respectively.
***
6369888
The transfer of the reticle pattern onto the photoresist layer is performed conventionally by an optical exposure tool such as a scanner or a stepper, which directs light or other radiation through the reticle to expose the photoresist.
***
6900001
In one example, exposure is done via an ArF laser, i.e. at a wavelength of from about 193 nm.

常圧CVD

常圧CVD
APCVD

6582777
Previous approaches to depositing such films have included plasma enhanced chemical vapor deposition (PECVD), electron cyclotron resonance plasma chemical vapor deposition, low pressure chemical vapor deposition (LPCVD) and atmospheric pressure chemical vapor deposition (APCVD), sub-atmospheric chemical vapor deposition (SACVD) or high density plasma chemical vapor deposition (HDP-CVD) using Si precursors.

シリコン酸化膜(二酸化ケイ素膜)

シリコン酸化膜(二酸化ケイ素膜)
silicon dioxide film

5000113
After depositing an .about.5.mu. thick silicon dioxide film on a wafer, the chamber can be cleaned in about one minute.
***
5614055
CVD formation of a thin silicon dioxide film on an integrated circuit structure having small (0.5 .mu.m or less) features with high aspect ratios (i.e., a large value of the ratio of channel depth to channel width, e.g., greater than two) is nearly impossible to accomplish without formation of voids between the metal lines.
***
5804259
Alternatively, the substrate may be moved from the load lock chamber to other chambers for subsequent processing without removing the substrate from the vacuum environment, e.g., moved to another chamber for PECVD formation of a carbon-based and/or silicon dioxide film thereon.

silicide

silicide
シリサイド（【化学】 ケイ素化合物, ケイ化物）

4778563
Thus, after patterning the silicide using a photoresist mask, the silicide can be used as the mask for etching the polysilicon, thereby providing precise pattern transfer to the polysilicon, independent of photoresist degradation.
***
5935877
The formation of these nitrides renders the silicide layer less sensitive and substantially decreases the silicide layer's normal rate of etch for an untreated surface.
***
5849092
One particular thermal CVD application is the deposition of tungsten or a tungsten-containing compound, such as tungsten silicide, over a semiconductor substrate from a process gas that includes tungsten hexafluoride and dichlorosilane or silane, and/or hydrogen and other gases.

electroplating

electroplating
電気めっき

6303523
Thereafter, copper 526 is deposited using either chemical vapor deposition, physical vapor deposition, electroplating, or combinations thereof to form the conductive structure.
***
6372633
Preferably, the metal is deposited using a low temperature process such as a combination of CVD followed by PVD or electroplating.
***
6790776
More particularly, the present invention relates to methods of forming a barrier layer and a seed layer prior to filling the structures formed on a substrate using an electroplating process.

dry oxidation

dry oxidation
ドライ酸化

6927169
Illustrative dry oxidation processes may be referred to herein a dry rapid thermal oxidation (RTO). Illustrative wet oxidation processes described herein are referred to as an in situ steam generation process (ISSG) and an external (or ex situ) steam generation process.
***
6159866
As illustrated in FIG. 8, reduced pressure steam oxidation processes provide for increased oxidation rates over dry oxidation processes at the same pressure.
***
6410456
Additionally, insitu steam generated oxidation processes with a H.sub.2 concentration greater than 3% provide higher oxidation rates than do dry oxidation processes at all oxidation pressures including atmospheric pressure.

photoresist

photoresist
フォトレジスト

6340435
A typical photoresist for silicon oxide layers is "RISTON," manufactured by duPont de Nemours Chemical Company.
***
6387819
After the first voids are etched, the voids are filled with a sacrificial material, such as a photoresist comprising an organic polymer, which is resistant to the etchant gas.
***
6171510
FIG. 1B shows a layer of photoresist 15 on the silicon oxide layer 11 that has been exposed and developed to form a window 16 in the photoresist.
***
5486235
The plasma was generated under the same conditions as those described for FIG. 2, but a potential reactive-species-generating material, a photoresist (Shipley 1400-33.RTM.)-coated silicon wafer was used to protect the substrate support platform.

anneal

anneal
熱処理（する）、アニール（する）

6472333
After the silicon carbide is formed on the organosilicate layer, the organosilicate layer is annealed.
***
6387761
However, such an anneal causes the oxidation of the underlying polysilicon electrode in the case of a capacitor and the oxidation of the underlying silicon substrate in the case of a MOS transistor.
***
6387761
Although a rapid thermal processor is preferably used to carryout the forming gas anneal of the present invention, the other well known apparatuses such as furnaces maybe used to anneal substrate 200, if desired.

ashing

ashing
アッシング（灰化除去）

6107192
The features can also contain residual photoresist on the feature surfaces from the photoresist stripping and/or ashing process or residual polymer from the dielectric etch step.
***
6211092
An unexpected feature of the integrated process is that it is preferred to strip the photoresist in the post-etch treatment (PET) or ashing step before the lower nitride stop layer is removed.
***
7144606
After etching, the photoresist layer is removed by exposing the photoresist layer to an active oxygen plasma, a process typically referred to as "ashing".

burn-in

burn-in
バーンイン

Currently, "BCS" or Burn-in/Conditioning/Seasoning is the process employed to control the lid/showerhead temperature.
6433314

Marangoni drying

Marangoni drying
マランゴニ乾燥

6746544
A conventional Marangoni drying system is disclosed in European Application number 0 385 536 Al, titled "Method and Arrangement for Drying Substrates After Treatment In a Liquid."
***
6955516
A method known as Marangoni drying creates a surface tension gradient to induce bath fluid to flow from the substrate in a manner that leaves the substrate virtually free of bath fluid, and thus may avoid streaking, spotting and residue marks.
***
6899111
Marangoni drying is a process whereby surface tension-reducing volatile organic compounds (VOC's) are passively introduced (by natural evaporation and diffusion of vapors) in the vicinity of the meniscus of a thin film of liquid adhering to a substrate in motion relative to the liquid.

IPA

IPA
isopropyl alcohol（イソプロピルアルコール）

7021319
In order to enhance the rinsing of the wafer, in an embodiment of the present invention a solution having a lower surface tension than water, such as but not limited to isopropyl alcohol (IPA) is dispensed in liquid or vapor form onto the wafer after the DI water.
***
6869516
In another aspect, the method includes positioning a substrate on a substrate support member having one or more electrical contacts, chemically plating a metal layer on at least a portion of a surface of the substrate, removing the processed substrate from the support member, and cleaning the one or more electrical contacts by spraying a vapor mixture comprising a mixture of isopropyl alcohol (IPA) and nitrogen on the one or more electrical contacts.
***
6541401
FIG. 2 shows scanning electron micrograph cross-sections of the surface morphology of SiO.sub.2 on untreated SiN film (FIG. 2A), on H2O2-pretreated SiN film (FIG. 2B) and on either IPA- or acetone-pretreated SiN (FIG. 2C).

bevel cleaning

bevel cleaning
ベベル洗浄

6691719
Adjustable nozzle for wafer bevel cleaning
***
6986185
For example, the brushes 15a-b may be positioned so as to be closer together on one end than on the other end (e.g., for bevel cleaning).

wet cleaning

wet cleaning
ウェット洗浄

6136211
In the competitive semiconductor industry, the increased cost per substrate that results from the downtime of the etching chamber, during the dry or wet cleaning, and seasoning process steps, is highly undesirable.
***
6380096
Although wet cleaning is relatively effective at providing clean surfaces for the next step, it is a slow and labor-intensive process inconsistent with the trend to automated, clean-room processing.
***
6098637
Another method of cleaning a ceramic chuck is a wet cleaning process which requires the system to be first vented to atmospheric pressure, then opened, cleaned, and subsequently returned to vacuum.

excimer laser

excimer laser
エキシマレーザ

5904776
Preferably openings are created through an overlying alumina dielectric layer using an excimer laser rather than a CO.sub.2 laser since the alumina is relatively transparent to the CO.sub.2 laser.
***
6460369
The light source generally used for such annealing processes for poly silicon films is an Xenon-Chlorine (XeCl) excimer laser.

tie bar

tie bar
タイバー

6270582
The wafer seats 140, 142 provide support for the wafers and also raise and lower the wafers in response to the action of a wafer lift apparatus that generally includes two guide rods 144, a tie bar 146 and a lift actuator 148.
***
6000227
The wafer lift apparatus for the embodiment shown in FIG. 5 has an air cylinder 148 for a lift actuator attached to a tie bar 150.

molding

molding
モールディング、封止

5533923
In instances where the matrix 322 molding process will place high pressures on tubulars 320 during molding, it may be desirable to have tubulars 320 filled with a solid material 324 which can subsequently be dissolved away after the molding process.
***
5900064
The various components in the process chamber 14, and the chamber itself, can be made from a variety of materials including metals, ceramics, glasses, polymers and composite materials, using conventional machining and molding methods.
***
7070480
Illustrative techniques include cutting, milling, molding and the like.

low dielectric constant film

low dielectric constant film
低誘電率膜

6287990
A method and apparatus for depositing a low dielectric constant film by reaction of an organosilane or organosiloxane compound and an oxidizing gas at a low RF power level from 10-250 W.
***
6583071
And as mentioned above, low dielectric constant films are particularly desirable for premetal dielectric (PMD) layers and intermetal dielectric (IMD) layers to reduce the RC time delay of the interconnect metalization, to prevent cross-talk between the different levels of metalization, and to reduce device power consumption.
***
6815373
Embodiments of the invention include a method for depositing a low dielectric constant film having a dielectric constant of about 3.5 or less, preferably about 3 or less, by blending one or more cyclic organosilicon compounds, one or more aliphatic organosilicon compounds, and one or more low molecular weight aliphatic hydrocarbon compounds.

dielectric constant

dielectric constant
誘電率

6303523
In order to further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and insulators having low k (dielectric constant <4.0) to reduce the capacitive coupling between adjacent metal lines.
***
6136685
Lowering the dielectric constant of insulating layers between conductive layers would reduce these undesired effects by reducing the capacitance.
***
6070551
With the advent of multilevel metal technology in which three, four, or more layers of metal are formed on the semiconductors, another goal of semiconductor manufacturers is lowering the dielectric constant of insulating layers such as intermetal dielectric layers.

in alignment with

in alignment with
一直線になって、一直線上に

5738574
Once the wafer 40 is in alignment with the wafer head 110, as shown in FIGS. 47D and 26C, the wafer is positioned below the recess 1115 of the lower portion 1110 of the wafer head 110.
***
6136163
Seals 837, such as O-rings, are disposed in the annular manifold channel 843 in alignment with the inlet 842 and outlet 854 and secured by the wafer holder plate 832 to ensure an airtight seal.
***
7158221
In cases where the XY stage assembly 106 is not in alignment with the substrate alignment feature, the XY coordinates from the XY stage assembly 106 can be mathematically transformed, or rotated, to obtain a corresponding XY coordinate of the physical location of the measurement on the substrate 114 relative to the substrate alignment feature.

diffusion

diffusion
拡散

6054379
For example, many low k dielectric materials are porous and are preferably protected by liner layers to prevent diffusion of metals.
***
5843847
For example, the dielectric layer can be deposited on a monocrystalline silicon substrate; a polysilicon layer on the substrate; or on anti-reflective or diffusion barrier layers, such as titanium silicide or titanium nitride.
***
6171661
The polishing of copper that is deposited over a diffusion barrier can therefore result in portions of the copper being undesirably peeled away from the surface of the diffusion barrier.

pattern defect

pattern defect
パターン欠陥

6987873
On the other hand, the classification of a defect as a particular type of pattern defect 2A (i.e., crater 3A, missing pattern 3B, extra pattern 3C, or deformed pattern 3D) implies that the foreign material is no longer present on the wafer, and only its effect is visible.
***
6353222
FIG. 11 shows a height contour of a pattern defect.

metal wiring

metal wiring
金属配線

6217721
An upper metal wiring layer is typically deposited simultaneously with the vertical interconnect beneath it.
***
5989623
Yet another technique for metal wiring of copper comprises the patterning and etching of a trench and/or contact within a thick layer of insulating material, such as SiO.sub.2.
***
6806203
Afterwards, formation of the dual damascene structure is completed by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material.

CMP

6168726
A soft dielectric is disadvantageous for advanced processing which is expected be based on damascene or dual-damascene structures and to use chemical mechanical polishing (CMP) to remove excess metal over a dielectric layer patterned to also receive the metal in via holes and interconnect trenches.
***
6582777
For subtractive processing, the dielectric material may be capped with an SiO.sub.2 layer for chemical mechanical polishing (CMP) to achieve global planarization.
***
5533923
The present invention pertains to chemical-mechanical polishing (or chemical-mechanical planarization) (CMP) of a semiconductor substrate and device materials upon that substrate.
***
6379223
Chemical-mechanical polishing (CMP) techniques and apparatus therefor have been developed for providing smooth topographies, particularly on the surfaces of layers deposited on semiconductor substrates during integrated circuit manufacture.
***
6207222
Referring to FIG. 1E, the top portion of the structure 10 is then planarized, preferably by chemical mechanical polishing (CMP).
***
6284149
Chemical mechanical polishing (CMP) is then performed to remove all of the metallization above the upper dielectric surface 26.
***
7041599
High through-put Cu CMP is achieved with reduced erosion and dishing by a multi-step polishing technique.
***
6380096
Chemical mechanical polishing (CMP) is applied to the top surface of the wafer. CMP removes the relatively soft exposed metal but stops on the relatively hard oxide layer 20.
***
5964653
A CMP process is fairly complex, and differs from simple wet sanding. In a CMP process, the reactive agent in the slurry reacts with the outer surface of the substrate to form reactive sites. The interaction of the polishing pad and the abrasive particles with the reactive sites results in polishing.
***
6709316
In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing pad. The pad is moved relative to the substrate by an external driving force. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing pad while dispersing a polishing composition to effect both chemical activity and mechanical activity.
***
6299741
An effective CMP process not only provides a high polishing rate, but also provides a substrate surface which is finished and flat.
***
6037257
The wafer is then subjected to chemical mechanical polishing (CMP) to remove all copper exposed above the top of the trench and thus to leave a copper interconnect in the trench.

dual damascene No.02

Integration scheme for dual damascene structure
6,753,258より引用

However, typical low k dielectric materials are generally porous and generally require a barrier layer to prevent interlayer diffusion of materials into the low k dielectric materials. The barrier layer comprises conventional barrier materials, such as silicon oxide and silicon nitride, that have dielectric constants greater than 4.0 and often greater than 7.0. The resulting insulator stack of low k dielectric materials and conventional barrier materials may have a dielectric constant that is not much below 6.0 which minimizes the use of low k dielectric materials as intermetal dielectric layers.

Copper is also being used to improve the current density of semiconductor devices. Copper (Cu) is becoming the interconnect material of choice because of copper's low resistivity (1.7 .mu..OMEGA.-cm) and high current carrying capacity. However, copper diffuses more readily into surrounding materials and can alter the electronic device characteristics of the adjacent layers and, for example, form a conductive path between layers, thereby reducing the reliability of the overall circuit and may even result in device failure.

multilayered

multilayered
多層の

6080529
This etch chemistry is especially useful in a multilayered substrate of the kind described above.
***
6759309
Because the interconnect is sealed within a multilayered sandwich and is difficult (if not impossible) to repair, it is important to obtain a robustness of these interconnects which is higher than wire bonding.
***
6494958
In another version, a multilayered or laminated dielectric 210 may be provided.

metalization

metalization
メタライゼーション

7104869
A barrier layer 405 of a conductive material, such as tantalum or a tantalum-containing material for copper metalization, is deposited in conformation in openings 411 and on the field 412 of the substrate, the upper surface of the dielectric layer 410.
***
5639357
The three phase sequence is repeated many times until the desired overall thickness of metalization is achieved.
***
6440864
These residues may cause problems during subsequent processing steps, such as trench patterning after a via etch or metalization of an etched structure.

gold plating

gold plating
金めっき

5317492
The nickel barrier was applied using standard electroless nickel plating techniques, and then the high purity gold was applied by gold plating.
***
6494959
In one embodiment, the reflector 112 comprises a gold plating on a surface of the cleaning apparatus 100 that faces the first surface 134 of the silicon wafer 132.
***
6822185
Moreover, the refractory material of the sensor is partially reflective, and can be made even more reflective by the addition of gold plating.

insulating film

insulating film
絶縁膜

6136685
An insulating film with a low dielectric constant is more quickly formed on a substrate by reducing the co-etch rate as the film is deposited.
***
5882399
A titanium nitride barrier layer may be applied on an interlayered insulating film (or over a titanium layer which has been applied to the insulating film), followed by formation of a titanium film over the titanium nitride film, and finally by formation of the aluminum film over the titanium film.
***
6245653
In another embodiment of the invention, a method for filling an opening in an insulating layer is disclosed, wherein, after forming at least one opening in an insulating film, a barrier layer is formed at least on an inner wall of said opening.

insulating layer

insulating layer
絶縁層

5028565
An insulating layer, such as a silicon oxide layer, which has been previously patterned to provide openings or vias to underlying portions of the integrated circuit structure formed in the silicon substrate will usually have been formed over the underlying silicon substrate and the integrated circuit structures formed therein.
***
5540800
A conventional insulating layer 81 may be employed to electrically insulate the Faraday shield and the coiled antenna 45 from one another.
***
5288665
Aluminum has been used for a number of years as interconnect material, as well as a filler material for vias in an insulating layer to provide electrical communication to either another metal interconnect layer or to underlying integrated circuit structure, e.g. , between different levels of interconnects or to contacts of an active device such as a bipolar or MOS transistor.

polysilicon

polysilicon
ポリシリコン

5556501
For example, etching of polysilicon requires low energy particles and low energy bombardment to avoid etching any oxide.
***
6074954
A preferred method of the invention, used to perform recess etchback of a polysilicon-filled trench in a substrate, comprises the following steps: a) providing --.
***
6081334
It is desirable to stop the etching process on the gate oxide layer because polysilicon can undergo charge damage and lattice structural damage upon exposure to the energetic plasma ions.

bonding

bonding
ボンディング

5737178
During such bonding processes, or afterward during use of the chuck in an erosive process environment, the joining material thermally or chemically degrades causing failure of the chuck and/or movement or misalignment of the substrate during processing.
***
5691876
This second transition temperature range functions as a process window for effective bonding of the Kapton.RTM. KJ to a metallic substrate such as conductive support platen 110 (typically constructed of stainless steel).
***
5545289
The ease of bonding of the nitrogen electron pair with the metal of the features 22, increases with the degree of alkyl substitution in the amine.

dicing

dicing
ダイシング

6759309
As in other prior art, the assembly and subsequent contacting of the ICs in the stack is done after dicing of the chip or chip arrays out of the silicon wafers.
***
6475326
For example, in applications where a wafer-sized structure is bonded and chips are later diced out of the wafer, the electrode contact areas can be removed during the dicing operation.
***
6790707
Following dicing, the side edge 410 of the test specimen 408 must be polished in order to eliminate defects from the side edge of the test specimen.

electro-migration, electromigration

electro-migration, electromigration
エレクトロマイグレーション

6139698
The (111) orientation is associated with the strongest aluminum film electro-migration resistance characteristics and is therefore preferred.
***
5242860
When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.
***
5378660
Further it has been found that the use of such equipment ensures better control of film quality which may have potential impact on the electromigration and other device performance properties.

damascene process

damascene process
ダマシンプロセス

6458516
This etch chemistry is particularly useful when the conductive material in a multilayered etch stack is copper, or when copper is the conductive fill material used for formation of a contact via, or in a damascene or dual damascene process.
***
6211092
The more conventional self-aligned dual-damascene process will be described first.
***
5968847
One of the preferred technologies for the formation of copper lines and copperfilled contact vias (plugs) is known as the damascene process.

tungsten plug

tungsten plug
タングステンプラグ

6372633
Next, the substrate was moved into a CMP system where the W was removed from the field of the substrate to form a thin tungsten plug in the recess formed in the via.
***
6162715
A gate electrode connection structure formed by deposition of a tungsten nitride barrier layer and a tungsten plug, where the tungsten nitride and tungsten deposition are accomplished in situ in the same chemical vapor deposition (CVD) chamber.
***
6183614
Two series of tests were performed to demonstrate an integrated process combining the Ti/TiN barrier deposited with the arced magnetron of the invention and a tungsten plug deposited by chemical vapor deposition (CVD) into the barrier-coated hole.

barrier metal

barrier metal
バリアメタル

5989623
Thereafter, a thin layer of a barrier metal, such as Ti, TiW or TiN, may be provided on top of the insulating layer and within the trench and/or contact to act as a diffusion barrier to prevent inter-diffusion of the metal to be subsequently deposited into the silicon, and between such metal and oxide.
***
5985033
Additionally, some processes use a barrier metal film that is, for example, formed of titanium and titanium nitride that covers the entire substrate surface wherein the titanium layer is partially exposed.
***
7026175
There are several other mechanisms for void creation, such as etch residues at the bottom of a small hole, poor adhesion of a via copper plug or trench copper line to the underlying barrier metal, void agglomeration due to copper recrystallization, and electromigration.

dual damascene No.01

dual damascene（デュアルダマシン）についての明細書の中で、技術的な背景から丁寧に説明しているものを以下にとりあげた。
英語の表現に加えて、技術面の勉強に役立つと思う。

Integration scheme for dual damascene structure
6,753,258より引用

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates to the fabrication of integrated circuits and to a process and apparatus for forming semiconductor devices on a substrate.

2. Background of the Related Art

Consistent and fairly predictable improvement in integrated circuit (IC) design and fabrication has been observed in the last decade. One key to successful improvements in IC design and fabrication is the multilevel interconnect technology which provides the conductive paths in an IC device. The shrinking dimensions of conductive or semiconductive substrate features such as horizontal lines and vertical contacts, vias, or interconnects, in very large scale integration (VLSI) and ultra large scale integration (ULSI) technology, has increased the importance of improving the current density of semiconductor devices.

In order to further improve the current density of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and low dielectric constant (low k) materials (defined herein as having dielectric constants, k, less than about 4.0) as insulating layers to reduce the capacitive coupling between adjacent interconnects. Increased capacitative coupling between layers can detrimentally affect the functioning of semiconductor devices.

titanium nitride

titanium nitride
窒化チタン

5043300
The nitrogen atmosphere used in this annealing step results in the simultaneous formation of a titanium nitride layer as the titanium reacts with the silicon to form titanium silicide.
***
5043300
This titanium nitride acts as a blocking layer to prevent migration of silicon atoms to the surface, from the underlying silicon.
***
5399237
A process for etching titanium nitride on a substrate 20 is described.
***
5882399
Titanium nitride layers have been used in semiconductor device structures as barrier layers for preventing the interdiffusion of adjacent layers of materials such as aluminum and silicon, for example.
***
5882399
However, the crystal orientation of aluminum deposited over the surface of the titanium nitride barrier layer is typically polycrystalline, and polycrystalline aluminum has poor electromigration resistance.
***
5250467
A titanium nitride layer is formed over the titanium silicide and on the surfaces of the insulation layer, including the top surface of the insulation layer and the sidewall surfaces of the contact openings through the insulating layer.

passivation

passivation
パッシベーション

5908672
A planarized passivation layer of the present invention preferably includes a fluorosilicate glass (FSG) layer and a silicon nitride layer.
***
6372633
A passivation layer, such as a silicon nitride (SiN) layer or other passivation layer, is preferably deposited over the resulting structure according to known techniques in the art.
***
6372633
A passivation layer 44, such as a silicon nitride layer, is then deposited conformally over the feature as shown in FIG. 12.
***
6821909
There is a need, therefore, for a method for selectively depositing a passivation layer on a conductive substrate using one or more electroplating techniques.
***
6821909
Embodiments of the invention provide a method for depositing a passivation layer on a substrate surface using one or more electroplating techniques.
***
6821909
A passivation layer is next deposited on the exposed initiation layer by a selective electroless deposition process in step 130.

----

passivation：
ICチップを機械的応力や不純物の侵入から保護すること。
（巴商会の半導体用語より引用）

via hole

via hole
ビアホール

6217721
FIG. 1 is a schematical cross-sectional view of a contact or via hole extending through a dielectric layer in a semiconductor integrated circuit.
***
6451703
A plasma etching step uses the patterned photoresist layer as a photomask to etch through the dielectric layer 14 to the underlying metal feature 12 to form a via hole 20.
***
6066892
A via hole 56 is photolithographically etched through the second dielectric layer 54 down to the underlying metal line 52.
***
6949203
Next, an extended via hole is etched from the top of trench dielectric layer 20 to the top of barrier layer 12 using a multistep etch process that must etch very deeply.

ion implantation

ion implantation
イオン注入

5886355
Thus ion implantation, which can drive ions into a wafer in an anisotropic manner, has become the doping method of choice for the manufacture of modern devices.
***
4587432
Tight control of water doping can best be achieved using ion implantation techniques and equipment. The uniformity of doping achievable only with ion implantation is critical in the fabrication of smaller geometry devices.
***
5262652
Thus ion implantation, which can drive ions into a wafer in an anisotropic manner, has become the doping method of choice for the manufacture of modern devices.

tungsten film

tungsten film
タングステン膜

6162715
If however, the tungsten film is used for a gate structure, low resistivity is a primary concern and WF.sub.6 flow is set to 36 sccm while H.sub.2 flow is increased to 1800 sccm.
***
5705080
In an exemplary seasoning process, the second step is carried out for about 120 seconds, to afford a tungsten film having a thickness of about 12,000 .ANG. Without the first seasoning step, the tungsten would not adhere well to the shadow plate.
***
6218301
The invention relates to a method of tungsten film deposition and, more particularly, to a method of forming a tungsten film having good film morphology and low resistivity.

barrier film

barrier film
バリア膜

6436267
the processing chamber 360 may be a PVD chamber configured to deposit a barrier film
***
7183197
Therefore, a good encapsulation/barrier film also requires low water vapor transmission rate (WVTR).
***
6368880
For deposition of a nitrated barrier film, such as tantalum nitride or tungsten nitride, the processing gas typically comprises an inert gas such as argon and a nitrating gas such as nitrogen, wherein --.

cobalt silicide

cobalt silicide
コバルトシリサイド

6899816
In one aspect, the cobalt layer is then annealed by a two-step annealing process to form cobalt silicide.
***
6740585
For example, a layer of cobalt is sputtered onto silicon, typically patterned on a substrate surface, and then subjected to a thermal annealing process to form cobalt silicide (CoSi).
***
6149784
For these reasons, cobalt silicide has been more extensively investigated as a replacement for titanium silicide.

sputtering

5962923
The filling of apertures using traditional sputtering methods has become difficult as the aperture aspect ratio has increased.
***
5371042
For example, combinations of varying sputtering rates and substrate temperatures have been tried in an effort to combine sputtering and melting of the aluminum-containing film so that the aluminum will at least partially melt and flow, thereby forming a continuous film in the opening.
***
5108570
The first step is carried out by sputtering from about 200 to about 2000 Angstroms of aluminum while the wafer temperature is within a range of from about 50.degree. C. to about 250.degree. C. and the sputtering plasma is at a power of from about 1 to about 16 kilowatts.

anisotropic dry etching

anisotropic dry etching
異方性ドライエッチング

4962063
Thus, wafer or substrate 10 may be processed by ECR deposition, CVD deposition, and anisotropic dry etching without leaving the vacuum apparatus for purposes both of preventing contamination as well as enhancing process efficiency.
***
6962514
The component etching may be carried out using a process known in the art for etching silicon, preferably, by anisotropic dry etching.
***
6378378
The receptacles are formed using an anisotropic dry etching technique, such as a reactive ion-etching technique, in the case where the substrate is a silicon wafer, but may be machined or otherwise formed if the substrate is made of printed circuit board material, for example.

self-aligned

self-aligned
セルフアライン、自己整合

5965035
An oxide etch process that is highly selective to nitride, thereby being beneficial for a self-aligned contact etch of silicon dioxide to an underlying thin layer of silicon nitride.
***
6284149
In the self-aligned technique, the substrate 10 and the metallization 12 are then covered with a lower stop layer 14, a low-k lower dielectric layer 16, and an upper stop layer 18.
***
6211092
There are two general types of dual-damascene processes, self-aligned and counterbore. The more conventional self-aligned dual-damascene process will be described first.

etch back

etch back
エッチバック

5000113
Secondly, the conformal oxide-forming thermal CVD step can be applied to existing dielectrics followed by an isotropic etch step to etch back any remaining non-planarities to a planar topography.
***
6080529
The excessive conductive material (not shown) overlying the mask patterning layer 222 (and mask patterning layer 222, if desired) is then removed either by etch back or by chemical-mechanical polishing.
***
4793897
Also, it may be possible to extend the process to planar deposition of plasma silicon dioxides over polysilicon or aluminum lines using deposition and etch back.

birefringence

birefringence
複屈折

7079740
If the lower cladding is too thin, the two orthogonal modes see a different effective refractive index resulting in birefringence, a consequential dispersion phenomenon that would limit the width of the transmission window.
***
7080528
For example, the refractive index along the direction of the stress can be different from the refractive index perpendicular to it, causing light polarized along the direction of the stress to propagate at a different rate than light polarized perpendicular to the direction of the stress. This phenomena is sometimes referred to as birefringence, and can lead to distortion of the optical signals in a fiber.
***
6958814
The stress can cause birefringence, leading to a change in polarization of one of the reflected components relative to another.

optical proximity correction

optical proximity correction
光学近接効果補正

6466314
Alternatively or additionally, said plurality of pattern-features comprise optical proximity correction (OPC) patterns.
***
6607634
The use of optical proximity correction (OPC) structures that are generally needed to minimize lines for shortening and corner rounding have necessitated significantly smaller features to be etched into the chrome.
***
7135344
Alternatively or additionally, generating the PDP includes determining an optical proximity correction (OPC) to be applied at the site, and selecting the site responsively to the OPC.

Phase Shift Mask

Phase Shift Mask
位相シフトマスク

Another method for increasing the resolution of the image is the use of RET (Resolution Enhancement Techniques) which include: off axis illumination, OPC (Optical Proximity Correction) reticles, and PSM (Phase Shift Mask) reticles.
6268093

resist

resist
レジスト

6541164
An anti-reflective coating (ARC) 18 is disposed over the tungsten silicide layer 22 and a resist (i.e., a photoresist or photomask), generally illustrated as 20, is patterned for being selectively positioned on the ARC 18, as best shown in FIG. 1.
***
6984579
The interconnect opening 106 may be formed by depositing a resist such as a photoresist 108 on the layer of nanotubes 104, patterning the photoresist 108, and etching the layer of nantotubes 104 using the photoresist as a mask.
***
6897941
A high resolution and high data rate spot grid array printer system is provided, wherein an image is formed by scanning spot-grid array of optical beams across a substrate layered with a resist.

lithography

lithography
リソグラフィ

4376672
Important contributors to achieving increased levels of device integration have been improvements in lithography technology and etching technology which are at the heart of all semiconductor IC fabrication.
***
4962063
It is very difficult to pattern further layers over such an uneven surface using standard lithography techniques.
***
4728389
Some of the most dramatic advances in manufacturing equipment have involved improved apparatus for lithography and etching.

buffer chamber

buffer chamber
バッファ室

6107192
A first robot 164 is typically positioned in a buffer chamber 168 to transfer substrates between the cassette loadlock 162, degas wafer orientation chamber 170, RPS preclean chamber 172, HP-PVD Ti/TiN chamber 175 and a cooldown chamber 176.
***
5186718
The system includes a housing 22 which defines four chambers: a robot buffer chamber 24 at one end, a transfer robot chamber 28 at the opposite end, and a pair of intermediate processing or treatment chambers 26 and 27.
***
5996353
The buffer chamber 203 has two expansion chambers 232 for performing additional processes on the substrates. The buffer chamber 203 may further have an optional cool-down chamber 234 for further cooling the substrates if necessary.

Johnsen-Rahbek

Johnsen-Rahbek
ジョンソンラーベック

6108189
It is known to use ceramic layers to fabricate the low conductivity Johnsen-Rahbek electrostatic chucks.
***
5909355
As such, the resistivity of the chuck is reduced to a value that facilitates establishment of the Johnsen-Rahbek effect and promotes wafer processing at room temperature.
***
6280584
The opposing accumulated electrostatic charges results in Coulombic or Johnsen-Rahbek electrostatic attractive forces which hold the substrate 100 to the chuck 15.

turbo-molecular pump

turbo-molecular pump
ターボ分子ポンプ

4911597
A turbo-molecular pump 31 connects chamber exhaust 32 to a remote pumping system (not shown) via exhaust line 33 for evacuating the processing camber 6 to subatmospheric pressure.
***
6503050
In one aspect, a vacuum processing system comprising a vacuum processing chamber and a turbo-molecular pump disposed on the vacuum processing chamber is provided.
***
5224809
A turbo-molecular pump 31 connects chamber exhaust 32 to a remote pumping system (not shown) via exhaust line 33 for evacuating the processing chamber 6 to subatmospheric pressure.

transfer chamber

transfer chamber
搬送室

5855681
More particularly, the present invention provides a staged vacuum system having one or more process chambers which share one or more utilities, one or more loadlock chambers and a transfer chamber connected to both the loadlock chambers and the process chambers.
***
5371042
The system 10 of FIG. 3 is a multichamber apparatus comprising two independently operated loadlock chambers 20 and 21 for loading and unloading semiconductor wafer cassettes into the first wafer transfer chamber 22.
***
6107192
A second robot 178 is located in transfer chamber 180 to transfer substrates to and from the cooldown chambers 176, a PVD IMP Ti/TiN chamber 182, a CVD Al Chamber 184, a CVD TiN chamber 186, and a PVD HTHU Al chamber 188.

Critical Dimension

Critical Dimension
ＣＤ

6388253
The design rule limitation is referred to as the critical dimension ("CD"), defined as the smallest width of a line or the smallest space between two lines permitted in the fabrication of the device.
***
6911399
The critical dimension (CD) microloading of the dense and the isolated regions can be eliminated and the photoresist trimming rate can also be reduced to enable better critical dimension (CD) control.
***
6451703
If the facets 22 reach the underlying upper dielectric layer 14, that is, the photoresist etching margin reaches zero, the critical dimension (CD) associated with the photomask is lost, and the upper portions of the via hole 20 become flared.

Front Opening Unified Pod

Front Opening Unified Pod
ＦＯＵＰ（フープ）

6902947
Also coupled to atmospheric transfer chamber 610 are a front opening unified pod 622 which transfers substrates into atmospheric transfer chamber 610, and a front opening unified pod 624 which transfers finished substrates out of atmospheric transfer chamber 610.
***
6897146
A preferred embodiment for depositing Cu barrier and seed layers on a semiconductor wafer comprises a front opening unified pod(s), a single wafer loadlock chamber(s), a degas chamber(s), a preclean chamber(s), a Ta or TaN process chamber(s), and a Cu process chamber(s).
***
6698991
If the wafer carrier is a sealed pod (e.g., a Standard Mechanical Interface (SMIF) pod), or a Front Opening Unified Pod (FOUP), the tool loading platform 425 comprises a mechanism for opening the same without exposing the wafers to the surrounding atmosphere, also as is known in the art.

Reactive Ion Etching

Reactive Ion Etching
反応性イオンエッチング

4842683
The present invention relates to a magnetic field-enhanced etch reactor suitable for both plasma etching and reactive ion etching (RIE) mode plasma etching and, to associated processes for etching semiconductor, conductor and dielectric materials.
***
5607542
A method and apparatus for generating a medium density plasma in a reactive ion etching chamber. A conventional reactive ion etching technique, using multiple electrodes for capacitive coupling of power into the chamber to establish and sustain a plasma, is combined with inductive coupling for plasma enhancement only.
***
6054379
The interconnects and contacts/vias are then etched using reactive ion etching or other anisotropic etching techniques to define the metallization structure (i.e., the interconnect and contact/via) as shown in FIG. 8F.

contact hole

contact hole
コンタクトホール

6051286
Oxide layer 950 may act as a pre-metal dielectric or as an inter-level dielectric, but to provide electrical contact between levels a contact hole 954 is etched through oxide layer 950 to be filled with a metal such as aluminum.
***
5780357
The invention relates to methods and apparatus for sputter deposition of material into high aspect ratio, re-entry shaped contact holes in semiconductor substrates.
***
5968379
However, in advanced integrated circuits, contact hole 954 is narrow, often less than about 0.35 .mu.m, and has an aspect ratio of about 6:1 or greater.

connecting hole

connecting hole
接続孔

5522937
The through holes 207 have a counterbore 208 on their top side. Similarly, four through holes 204 in a bellows connecting hole pattern 141 include counterbores 205 around the holes as seen from the top side of the susceptor arm in FIG. 10.
***
6887786
If a lower layer to which a connection is made is the semiconductor substrate, then a connecting hole is referred to as a "contact"; if the lower layer is a metallization layer then the connecting hole is referred to as a "via".

hydrophilic, hydrophile

hydrophilic, hydrophile
親水性の

6267853
The exposed surfaces of the cathode contact ring, except the surfaces of the contact pads that come in contact with the substrate, are preferably treated to provide hydrophilic surfaces or coated with a material that exhibits hydrophilic properties.
***
6413583
Deposition of a hydrophobic liner layer has a surprising and unexpected result of converting subsequent hydrophilic gap filling layers to hydrophobic layers having good moisture barrier properties.
***
6583071
Typical surfactants exhibit an amphiphilic nature, meaning that they can be both hydrophilic and hydrophobic at the same time.

solubility

solubility
溶解度、溶解性

5812362
The solubility and diffusion of impurities or contaminants in diamond coating 110 according to any of the above methods are negligible.
***
6605394
Chemically amplified DUV photoresists require a post-exposure bake to uniformly diffuse the photogenerated acid within the exposed regions, and to complete the chemical transformations within these regions that affect differential solubility.
***
6440495
CVD precursors for advanced DRAM electrodes and dielectrics have traditionally been solid compounds and although soluble in organic solvents such as tetrahydrofuran, solubility is limited. CVD deposition of films can require high vaporization temperatures and residues are left after vaporization and deposition.

spin drying

spin drying
スピンドライ

6843855
Spin drying of the wafer 606 macroscopically dries the wafer 606.
***
5884640
Another advantage is that the substrates 55 are not subject to the stresses and potential damage associates with spin drying.

rinsing liquid

rinsing liquid
リンス液

6689418
This embodiment includes dropping the substrate front side down onto a pool of rinsing liquid in a manner such that the front side of the substrate is in contact with the solution while the substrate is held in suspension by the surface tension of the solution liquid thereby preventing the backside of the substrate from sinking under an upper surface of the pool.
***
6261157
Each of the polishing stations 25a, 25b, 25c also includes a fluid delivery arm 52 that serves to delivery both slurry (or a polishing liquid) and a rinsing liquid to the platens 30.
***
6571657
The pairs of substrates are then transferred to the SRD unit 2704 and/or the IBC unit to clean the surface of the substrate by rinsing the surface of the substrate with a rinsing liquid, or etch undesired deposits from the seed layer on the substrate by applying an etchant to the substrate.

plasma etching

plasma etching
プラズマエッチング

以下は、すべてApplied Materialsの明細書から引用。

6709609
The method includes exposing the substrate to a preheating plasma which produces a deposit or residue during preheating which is more easily etched than said metal-containing layer during the subsequent plasma etching of said metal-containing layer.
***
6642151
The present invention relates to processes, materials and devices for plasma etching of Si--Ge layers for fabricating optically smooth Si--Ge surfaces, and particularly to fabricating waveguides in opto-electronic integrated circuits employing Si--Ge.
***
4412885
This invention relates generally to reactive gas chemistry for plasma etching of layers of material used in fabrication of semiconductor integrated circuits and to methods for plasma etching of such materials.

a deposite (NOUN)

a deposite (NOUN)
付着物；沈澱[沈積]物、堆積物

以下は、すべてApplied Materialsの明細書から引用。

6709609
The method includes exposing the substrate to a preheating plasma which produces a deposit or residue during preheating which is more easily etched than said metal-containing layer during the subsequent plasma etching of said metal-containing layer.
***
6277251
The method of claim 7 wherein a deposit of a material is present on at least one of said deposition support members.
***
5788799
Thus, by controlling the temperature of a surface, it is possible to reduce deposition or prevent deposition, or to increase the decomposition rate and removal of a deposit from a surface.
***
6444101
Contact pins 56 shield only a small portion of the substrate surface area, some electrolyte solution passes to the backside of the substrate (passing between the substrate 48 and the contact ring 20), thus forming a deposit on the backside and the substrate holder 14.

deposit (VERB)

deposite
堆積させる

以下は、すべてApplied Materialsの明細書から引用。

6911403
Embodiments of the invention provide a method for depositing an organosilicate layer on a substrate such that plasma-induced damage to the substrate is minimized.
***
6824658
For example, to deposit materials onto a semiconductor wafer, substrate, or other workpiece using a sputter deposition process, a plasma is produced in the vicinity of a sputter target material which is negatively biased.
***
5932286
Thin, uniform films of silicon nitride can be deposited onto a single substrate in a low pressure chemical vapor deposition process at a practicable rate from a gas mixture including a silane precursor gas and ammonia by maintaining the pressure at between about 5 and about 100 Torr.

in situ

in situ
インサイチュの、インサイチュで

★「in-situ」：「元の位置に[の], 本来の場所に[の]」
【半導体分野】実際のプロセスが起こっている場所を意味するので、上記の訳のように、必ずしも「表面」とは限らない。むしろ、「in situ」（in-situ）のままで使われることが多い。また、半導体分野では、日本語的発音で「インサイチュ」などを使う。

以下の用例は、半導体製造装置で世界的に有名なApplied Materials, Inc.の明細書より引用した。

6217715
However, the layer will need to be replaced periodically and is conveniently deposited in situ in a vacuum processing chamber using the apparatus shown in FIG. 2.
***
6098637
The invention provides generally a method and an apparatus for in situ cleaning of a surface in a semiconductor substrate processing chamber which operates quickly and reduces the downtime for chamber cleaning.
***
4613400
It is another object of the present invention to provide an in-situ pre-etching procedure for forming a protective cap on an etch mask, which provides very high layer:mask etch selectivity.
***
6228781
Film stability is improved by subjecting the film to one or more in-situ heat treatment steps.
***
5814377
There is a need for improving the interface between the two layers while allowing the two processes to occur in-situ, or back-to-back, in the same chamber without an intermediate chamber cleaning step.
***
5952060
In another preferred embodiment, the carbon-based coating is applied and periodically reapplied in an in situ process between substrate processing steps.
***
6362115
A method and apparatus for forming thin polymer layers having low dielectric constants on semiconductor substrates includes in situ formation of p-xylylenes, or derivatives thereof from liquid precursors such as p-xylene, 1,4-bis(formatomethyl)benzene, or 1,4-bis(N-methyl-aminomethyl)benzene.
***
6356097
The invention relates generally to diagnostic instrumentation for semiconductor wafer processing equipment and, more specifically, to a capacitive probe for in situ measurement of the DC bias voltage accumulated on a semiconductor wafer while being processed in a semiconductor wafer processing system.
***
5899752
A method of in-situ cleaning a native oxide layer from the surface of a silicon wafer positioned in a vacuum chamber that is substantially free of oxidizing species by passing at least one non-oxidizing gas over the native oxide layer at a wafer cleaning temperature between about 650.degree. C. to about 1025.degree. C. for a sufficient length of time until such native oxide layer is removed.