特許の英語（特許翻訳分野）

関連して with respect to

このような従来のプロセスは、本技術分野ではよく知られており、図１Ｂに関連してすでに説明したとおりである。

Such conventional deposition processes are known in the art, as discussed above with respect to Figure1 B.

特許公表２００５－５０３０００
WO02065517より引用

＊「関連した」には、[associated]などがある。

be deposited at

このフィルム４２２（それ）は、約６００℃の温度で、厚さ約５００Åに成膜される。

It is deposited at a deposition temperature of about600 C and has a thickness of about 500A.

特許公表２００５－５０３０００
WO02065517より引用

成膜する

また、図１Ｂと１Ｃは、化学気相成長法でシランを使用することによって、基板１００にシリコンフィルムを成膜した結果を示す模式的断面図である。

Figures 1B and 1C schematically illustrate the results obtained by using silane in a chemical vapor deposition process to deposit a silicon film onto the substrate100.

特許公表２００５－５０３０００
WO02065517より引用

deposition [UC]

しかし、これらの従来のシリコン源を用いる成膜法では、通常、単結晶シリコンとシリコン酸化物の両者を含む表面のような混合基板への成膜をコントロールすることが困難である。

However, deposition using these conventional silicon sources is generally difficult to control over mixed substrates, such as surfaces containing both single crystal silicon and silicon dioxide.

特許公表２００５－５０３０００
WO02065517より引用

●deposition [UC] 堆積
（研究社　新英和中辞典より引用）

半導体分野で、翻訳を発注するお客により、「deposition＝堆積」、「deposition＝成膜」、あるいは「deposition＝成長」と指定する場合がある。
つまり、お客により指示する訳語がまちまちである。
このような時は、語学的や技術的に正しいかどうかで判断するのではなく、あくまでも、お客の指示に従うべきである。
翻訳者は、いわば床屋のようなものである。
お客が指示した髪型が「変」だと思っても、あくまでも、お客の指示に従うべきである。
ただし、翻訳済文章の後に、「翻訳メモ」のようなコーナーを作っておくと、後々、トラブルが少なくなる。
そのコーナーに、「○○は△△だと解釈しましたが、御社の指示どおり訳しました。」とメモを入れておけば、お客は、翻訳者は内容を理解しつつも、お客の指示に従っていることを理解してくれるので、この「翻訳メモ」を活用するとよい。

覆うように to cover

ガラス基板１５の上には、図１６に示すように、共通配線２３を覆うように絶縁膜２６が設けられている。

As shown in FIG. 16, an insulating film 26 is provided over the glass substrate 15 to cover the common lines 23.

特許公表２００７－５１６４６４
WO2005071477 （英文は日本人による翻訳：英文は参考程度に）
より

suitable for use as a xxx

ＵＳ ５ １３２ ８２３は、反射型ディスプレイ・オーバーヘッドプロジェクションパネルとして使用するのに適した、多目的ＬＣＤを開示している。

US 5 132 823 discloses a multipurpose LCD suitable for use as a reflective display and overhead projection panel

特許公表２００２－５１７７８１
WO9963395 （英文は日本人による翻訳：英文は参考程度に）
より

（～という）欠点がある #02

しかしながら、図１に示すＥＬデバイスは、赤色ＥＬ素子によって発せられる光がデバイスから発せられる前に、他の２つの素子を通過しなければならず、かつ緑色ＥＬデバイスから発せられる光が青色ＥＬデバイスを通過しなければならないという欠点を有する。

However, the EL device shown in Figure 1 has the disadvantage that light emitted by the red EL element must pass through the other two elements before it is emitted from the device, and that light emitted from the green EL device must pass through the blue EL device.

特許公表２００２－５３２８６５
WO0036881 （英文は日本人による翻訳：英文は参考程度に）
より

LCRメータ

LCRメータ
LCR meter
7089519
Cadence
To determine the coupling capacitances Ct, Cb and Cc, an LCR meter is first used to measure seven capacitances C1, C2, C3, C4, C5, C6, and C7.

FIB

FIB
focused ion beam
7089518
Cadence
One commonly used measurement technique uses a destructive methodology, where a focused ion beam ("FIB") cuts into a fabricated wafer exposing the cross section of an interconnect line and then a Scanning Electron Microscope ("SEM") takes pictures of the exposed interconnect line.

CBCM

CBCM
charge-based capacitance measurement
7089517
Cadence
The method of claim 1 wherein the test structure is in electrical communication with a charge-based capacitance measurement (CBCM) circuit.

フィールドソルバー

フィールドソルバー
field solver
7089516
Cadence
Independently, a field solver calculates initial coupling capacitances from initial process parameters.

BBD

BBD
block-based design
6631473
Cadence
To overcome the shortcomings of the available art, the present invention discloses a novel methodology and implementation for block-based design ("BBD").

VC

virtual component
6631472
Cadence
Today, logic previously contained in a whole chip is now used as a single virtual component (VC) or design block to be included in a larger chip.

Scan Design methodology

Scan Design methodology
6631471
Cadence
The available Scan Design methodology is a simple example of a highly effective and widely used method for applying a "single" test method to the entire chip with predictable and consistent test result.

DFT

DFT
Design for Test
6631470
Cadence
Before the advent of Design for Test ("DFT") methodologies, designers created and assembled a chip, then passed the completed design to test designers.

in-phase component

a computer aided design apparatus for defining

a computer aided design apparatus for defining
5663891
Cadence
In a computer aided design apparatus for defining a system, the apparatus including a database storing a structural description of the system, the structural description including a plurality of objects, each object having a binary relationship with at least one other object, a computer implemented method for optimizing at least one performance criteria of the system, where each performance criteria is described by at least one convex cost function, the method comprising:

ルーティング

ルーティング
routing
6543043
Cadence
In an electronic design automation system, a method for placement and routing, comprising the steps of: receiving a netlist file comprising a specification of logic cell instances and nets connecting said logic cell instances; placing said logic cell instances in a circuit layout by giving said logic cell instances specific coordinate locations in said circuit layout, said step of placing said logic cell instances comprising the step of defining a plurality of conduits separating said logic cell instances; locating said nets in said conduits; identifying a set of constraints associated with the nets placed in said conduits; and for each conduit, associating the nets placed therein with one or more tracks in the conduit using constraint information for both the conduit being processed and other nearby conduits, regardless of whether said other nearby conduits were previously processed or are as yet unprocessed.

インラインサブサーキット

インラインサブサーキット
inline subcircuit
6381563
Cadence
FIG. 5 is an illustration of a component having parasitic resistances and capacitances modeled therein that can be represented by an inline subcircuit according to the present invention.

リーフセル

リーフセル
leaf cell
5568396
Cadence
Current methods for identifying overconstraints are limited to leaf cells, and cannot identify overconstraints in hierarchical layouts.

SKILL Code

SKILL Code

5418954
Cadence
The SKILL Codes represent the actual source programs that may constitute a collection of files or procedural sequences or data which represent the selected functionality as a complete "executable."

*Note:
The SKILL language has been developed by Cadence to be used with their tool suites.

Virtuoso

Virtuoso

6671866
Cadence
ne example of such an editor is Virtuoso.RTM. Layout Editor, commercially available from Cadence Design Systems, Inc., of San Jose, Calif.

VCC

VCC
Virtual Component Codesign
6882965
Cadence
This framework is part of a Virtual Component Codesign (VCC) process, which is targeted at consumer embedded system design.

DFM

DFM
design for manufacturing
5539652
Hewlett-Packard Company
To achieve such quality control and defect reduction, there is an emphasis on design for test (DFT), design for quality (DFQ), and design for manufacturing (DFM) in the early design of electronic circuits.

ニッケルシリサイドゲート

ニッケルシリサイドゲート
nickel silicide gate
6913959
AMD
For example, the tensile stress of a nickel silicide gate is approximately 800 MegaPascals (MPa) when annealed at a temperature of 360.degree. C. and approximately 1.25 GigaPascals (GPa) when annealed at a temperature of 400.degree. C.

HBT

HBT
Hetero-Bipolar Transistor
7049893
M/A-COM, Inc.
This present invention relates generally to power amplifiers, and particularly to Hetero-Bipolar Transistor (HBT) power amplifier control.

ESL

ESL
electronic-system-level

Cadence
With the lofty goal of creating a new level of design abstraction, Cadence Design Systems and CoWare will jointly pursue an electronic-system-level (ESL) design methodology.

サファイヤ基板

サファイヤ基板
sapphire substrate
4214946
IBM
The Weitzel patent discloses a process for forming a blind hole having an isosceles trapezoidal cross-section in a sapphire substrate using a sulfur hexafluoride gas etchant and an etch mask of silicon nitride on top of silicon dioxide.

IGBT

IGBT
insulated gate bipolar transistor
4965710
International Rectifier Corporation
This invention relates to semiconductor device power modules, and more specifically relates to a novel power module employing insulated gate bipolar transistors ("IGBT") with self-contained driver and control circuits.

HEMT

HEMT
high electron mobility transistor
5140386
Raytheon Company
In general, one of the more common semiconductor devices used at these frequencies are field effect transistors, in particularly metal semiconductor field effect transistors (MESFETs) and high electron mobility transistors (HEMTs).

EDA

EDA
electronic design automation
6543043
Cadence
Chip designers often use electronic design automation (EDA) software tools to assist in the design process, and to allow simulation of a chip design prior to prototyping or production.

ネットリスト

ネットリスト
netlist
5084824
National Semiconductor
The gate-level netlist component of the simulation models are created automatically in a computer-implemented technique that identifies each root in the combinatorial circuit, assigns each a logical value, and traverses the tree that originates from each identified root.

設計フロー

PoP

PoP
Package on Package
7129726
Fujitsu
In an SiP (System in Package) which constitutes a system by accommodating a plurality of semiconductor devices in a single outer package (accommodation container), there is a PoP (Package on Package) which constitutes a single outer package by mounting other semiconductor devices on a back surface of one semiconductor device.

SOI

SoC

SoC
system on a chip
6301696
Actel
Furthermore, as will be discussed below, the present invention also teaches a method of making an integrated circuit (IC), such as a system on a chip (SOC), that includes an embedded FPGA.

SiP（システムインパッケージ）

GaN（窒化ガリウム）

GaN（窒化ガリウム）
Gallium Nitride
6987068
Intel
These combinations include Gallium (Ga) and Arsenic (As) to form Gallium Arsenide (GaAs), Indium (In) and Phosphorus (P) to form Indium Phosphide (InP), Silicon (Si) and Carbon (C) to form Silicon Carbide (SiC), and Gallium and Nitrogen to form Gallium Nitride (GaN).

アモルファス材料

アモルファス材料
amorphous material

3716844
IBM
It has been discovered here that highly absorbing thin films of amorphous materials such as Si, Ge, and SiC, when subjected to localized heating from a moderate intense laser or electron beam exhibit some degree of transparency even in the amorphous state and are substantially transparent in their crystalline state.

※amorphous
adj.
1 不定形の.
2 【結晶】 非晶質の, 非結晶質の, アモルファスな： 結晶した物質を含まない組織を指す. 例： amorphous silica 非晶質無水ケイ酸, amorphous graphite 土状黒鉛. cf. →crystalline.
（研究社　理化学英和辞典より引用）

キャップ膜

キャップ膜
capping film

6258707
IBM
The process as in claim 1, in which said step (b) includes forming a capping film on said upper surface of said dielectric film, said capping film having a capping surface and wherein said polished surface is substantially continuous with said capping surface.

SM

SM
stress migration ストレス･マイグレーション

6426544
IBM
The present invention generally relates to Integrated circuit structures and fabrication and, more particularly, to formation of wiring having improved resistance to electromigration and stress migration failure and high precision capacitors.

EM

EM
electro-migration, electromigration エレクトロマイグレーション

4234367
IBM
However, it was found that silver has a tendency to cause electro-migration problems and is suspected of diffusing into the glass-ceramic.

CoWP

CoWP
cobalt-tungsten-phosphorus

7005371
IBM
Other materials that may be used for encapsulating the interconnects include cobalt-tungsten-phosphorus (CoWP) and Ni--Au alloys, which may be deposited by electroplating and electroless plating, among other methods.

BGA

BGA
ball grid array

7049704
Intel
Ball Grid Array (BGA) package 106 is suitable for any integrated circuit 104 that may previously have been put in a plastic type package.

CSP

CSP
CSP、chip size package（チップサイズパッケージ）

6655022
Intel
The micro ball grid array (.mu.BGA) package is considered a chip size package (CSP). A chip size package is generally defined as a package which does not exceed the die size by greater than 20%.

エバネセント波

エバネセント波
evanescent wave

5220403
IBM
For example, as illustrated in FIG. 2a, a ray 210 propagating through the lens at an angle of 66.degree. from the normal to a silicon air interface, becomes an evanescent wave 212 which dies off as e.sup.-kz where k is given by equation ABCDE.

ポラリトン

ポラリトン
polariton

6075640
Massachusetts Institute of Technology
In another embodiment, the signal processing method includes: converting an input signals into a polariton that propagates in a non-conductive signal processing material;

プラズモン

プラズモン
plasmon

4249796
IBM
That light which is not reflected is converted into surface electromagnetic waves, either plasmons or polaritons, at the surface of the film.

ラマン分光（法）

ラマン分光（法）
raman spectroscopy

6975891
NIR Diagnostics Inc.
Raman spectroscopy is concerned with the phenomenon of a frequency change when photons of electromagnetic radiation are inelastically scattered by molecules.

UV硬化プロセス

UV硬化プロセス
UV cure process

6479411
In a preferred UV cure process, the substrate is placed in an enclosed treatment chamber under a UV source and heated for between 40 to 50 seconds.

歪みエンジニアリング技術

歪みエンジニアリング技術
strain engineering technology

Applied Materials, Inc. today announced the Applied Producer Celera (TM) PECVD(1), a significant advancement in strain engineering technology that achieves the stress levels required for manufacturing faster transistors in 45nm and beyond devices.

（Applied Materialsの記事より引用）

ALD

ALD
atomic layer deposition（原子層成長、原子層堆積）

7101811
Intel
Atomic layer deposition (ALD) refers to the controlled deposition of single atomic layers on a substrate.

酸化ハフニウム

酸化ハフニウム
hafnium oxide

7157378
Intel
The method of claim 1 wherein the high-k gate dielectric layer comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

45nmノード

45nmノード
45 nm technology node

6627362
Intel
Using this technique, a sensitivity of 45 nm may be achieved for a 45 nm technology node.

フォトマスクブランクス

フォトマスクブランクス
photomask blanks

6543617
IBM
Fast and high resoltuion resists that are exposable by electron beams or laser beams at all wavelengths are also vital for next generation production of photomask blanks (see "Positive Chemically Amplified Resist for Next Generation Photomask Fabrication" by T. Segaw et al., SPIE Proceed., 3236, 82-93 (1999)).

混載DRAM eDRAM

混載DRAM
eDRAM
embedded dynamic random access memory

7073139
IBM
A method for determining contact location for embedded dynamic random access memory (eDRAM) formed in a silicon-on-insulator (SOI) substrate includes reviewing contact design data for an eDRAM device and discarding contact locations corresponding to contact shapes within a support area of the eDRAM device.

ポーラスlow-k膜

ポーラスlow-k膜
porous low-k dielectric film

6514881
Texas Instruments
The invention is generally related to the field of pre- and inter-metal dielectric films used in integrated circuits and more specifically to porous low-k dielectric films.

混載DRAM

混載DRAM
mixed DRAM

6251751
IBM
This invention relates to forming bulk or strained Si/SiGe layered regions adjacent to or on an insulator and more particularly to local selective oxidation of SiGe for forming an insulator region underneath semiconductor regions for device applications such as complementary metal-oxide-semiconductor (CMOS) field effect transistors (FET's), modulation-doped field-effect transistors (MODFET's), dynamic random access memories (DRAM's), mixed DRAM and CMOS, static random access memories (SRAM's), BiCMOS, and rf.

先端プロセス

先端プロセス
leading process

7074714
Therefore, the leading process for formation of copper-comprising devices is a damascene structure, which requires the filling of embedded trenches and/or vias.

犠牲層

犠牲層
sacrificial layer

5302477
Intel
Sacrificial layer 90 can be any organic or inorganic layer which has a lower etch rate than the substrate and opaque layer in the respective etches of these materials.

high-kゲート絶縁層

high-kゲート絶縁層
high-k gate dielectric layer

7126199
Intel
Referring to FIG. 1, a stack, formed on a substrate 100, may include a high-k gate dielectric 180, a metal barrier layer 160, a workfunction setting metal layer 190, and a cap metal layer 115, in one embodiment. As used herein, high-k means having a dielectric constant greater than 10.

Intelにおいては、「high-kゲートxxx」の英文として、「high-k gate dielectric layer」が多く使われている。

high-kゲート絶縁膜

high-kゲート絶縁膜
high-k gate insulator

6271094
IBM
herefore, the development of a Complementary Metal Oxide Semiconductor (CMOS) technology which utilizes a high-k gate insulator is a must for the continuing of CMOS scaling into the sub-0.1 .mu.m regime.

「high-kゲート絶縁膜」について：

ゲート絶縁膜として「厚さがあり、かつ大量の電流を流せる高誘電率な素材」を「high-kゲート絶縁膜」と呼ぶのが一般的なようである。

high-k gate insulatorは、語学的には「high-kゲート絶縁体」なのであるが、実際には、「絶縁膜」の「膜」という用語のほうがはるかに多く使われている。

NGL

NGL
generation lithography

6894762
LSI Logic Corporation
As an alternative, next generation lithography (NGL) methods such as electron beam lithography, extreme ultraviolet (EUV), and x-ray lithography are able to print patterns with higher resolution.

半導体分野の企業の形態による名称

●IDM
(Integrated Device Manufacturer) A company that performs every step of the chip-making process, including design, manufacture, test and packaging. Examples of IDMs are Intel, AMD, Motorola, IBM, TI and Lucent.

●fab
A manufacturing plant that makes semiconductor devices. As of 2005, the top 10 semiconductor companies worldwide based on sales and ranked starting with the largest were Intel, Samsung, Renesas (Hitachi-Mitsubishi merger), Texas Instruments, Toshiba, Infineon, STMicroelectronics, NEC, Freescale and Philips.

●fabless
(FABricationLESS) A semiconductor vendor that does not have inhouse manufacturing facilities. Although it designs and tests the chips, it relies on external foundries (fabs) for their actual fabrication.

●foundry
A semiconductor manufacturer that makes chips for third parties. It may be a large chip maker that sells its excess manufacturing capacity or one that makes chips exclusively for other companies. No less than two billion dollars is needed to construct a twenty-first century, high-production semiconductor manufacturing plant.

（Answer Comより引用）

ダブルパターニング

ダブルパターニング
double patterning

7064078
In the double patterning method, a hardmask layer is deposited on a substrate layer that is to be etched. The hardmask layer is patterned by a photoresist deposited on the hardmask layer. The photoresist is then removed, and a second pattern is introduced into the hardmask layer with a second photoresist that is deposited on the hardmask layer.

ヘイズ欠陥

ヘイズ欠陥
haze defect

6106626
Taiwan Semincondutor Manufacturing Company
The fine powder of ammonium chloride deposits on top of a wafer surface and forms a haze defect. The nitride haze, once formed, is very difficult to remove from the wafer surface. For instance, a wet scrubbing method by using a brush cannot remove the haze from the wafer surface. The nitride haze acts as an additional insulating layer on top of the silicon wafer and presents processing difficulties in subsequently carried out processes.

TWからの出願なので、英文は参考程度に利用する。

ディープSiエッチング

ディープSiエッチング
deep Si etching

7139172
IBM
In one exemplary embodiment of the invention in which the substrate (41) is formed of silicon (Si), the fluid vias can be formed using a deep Si etching method to etch the fluid vias partially through the substrate (41).

WLP

WLP
wafer level packaging（ウエハレベルパッケージング）

6858466
Hewlett-Packard Development
The term "wafer level packaging" or "WLP" is meant to be understood as any IC or MEMS packaging technique in which packaging is formed at the wafer level.

ARC

ARC
Antireflective Coating（反射防止膜）

6291356
Silicon oxynitride is primarily used as an antireflective coating (ARC) and is often referred to as a "dielectric ARC".

COO

COO
Cost-of-Ownership（所有コスト）

6930033
Intel
A PVD process usually has a lower Cost-of-Ownership (CoO) than a CVD process.

LWR

LWR
line width roughness（ライン幅ラフネス）

7105398
IBM
According to the invention, there is provided a methodology that uses an in-line CD SEM to measure and flag issues in the dual spacer process by making a line width roughness measurement (LWR) in the region of interest (ROI).

HP

HP
half-pitch

reed electronics
Chemical shrink, trilayer resists, immersion lithography and double patterning are all viable options for getting to the 45 nm half-pitch (HP) using ArF illumination.

PVDF

PVDF
polyvinylidene fluoride（ポリフッ化ビニリデン）

6228231
IBM
Frame 34 preferably includes polyvinylidene fluoride (PVDF), polypropylene, PVC, or other suitable non-conductive material, further being resistant to corrosion from the electrolyte bath.

PVC

PVC
polyvinyl chloride（ポリ塩化ビニル）

6126798
IBM
Anode cup 202 is typically an electrically insulating material such as polyvinyl chloride (PVC), polypropylene or polyvinylidene flouride (PVDF).

PMMA

PMMA
poly(methyl methacrylate)  （ポリメチルメタアクリレート）

5547812
IBM
Microbridge formation in chemically amplified negative tone photoresists based on poly(hydroxystyrene) (PHS) is avoided when the PHS is blended together with a co-polymer of PHS and an acrylic polymer such as poly(methyl methacrylate) (PMMA).

PDMS

PDMS
polydimethylsiloxane（ポリジメチルシロキサン）

6537499
IBM
The biosensor comprises at least one pillar made of elastomeric material like polydimethylsiloxane (PDMS) having a diameter from about 0,1 .mu.m to 1 mm and an aspect ratio of about 2-10.

MOCVD

MOCVD
metal organic chemical vapor deposition（有機金属気相成長）

5543988
IBM
Layer 30 and semiconductor bar 14 may be deposited by an epitaxial technique including molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD) and liquid phase epitaxy (LPE).

LRC

LRC
lithography rule checker

7149340
LSI Logic Corporation
Taurus-LRC is a "lithography rule checker" that verifies that a final mask layout delivers the intended result on silicon.

SSOI

SSOI
strained silicon-on-insulator

6774015
IBM
Strained silicon-on-insulator (SSOI) and method to form the same

MRAM

MRAM
Magnetic Resistive Random Access Memory

6912892
Hewlett-Packard Development
the sample 124 includes a set of Magnetic Resistive Random Access Memory (MRAM) storage cells;

LPP

LPP
landing plug poly

7018924
Hynix Semiconductor Inc.
More particularly, the disclosed methods for forming metal line contact plugs can form a stable landing plug poly (LPP) by performing a polishing process of a multi-layer film by using the CMP slurry for oxide film including an HXO.sub.n compound (wherein n is an integer from 1 to 4).

KRからの出願（nativeではない）なので、英文は参考程度に使うこと。

電子ビーム検査

電子ビーム検査
electron beam inspection

7183546
During electron beam inspection of the SOI wafer each of the epilayer islands 230, 232 and 234 acts like a capacitor and is charged to a certain voltage level.

TSV

TSV
through-silicon via（Si貫通ビア）

7111149
Intel
Future memory devices may utilize new technologies in packaging stacked devices, such as through-silicon vias or optical technology.

ナノインプリントリソグラフィ

ナノインプリントリソグラフィ
nano-imprint lithography

7060625
Hewlett-Packard
Nano-imprint lithography is a promising technique for obtaining nano-size patterns (as small as a few tens of nanometers or less) in a media.

EBL

EBL
Electron Beam Lithography（電子ビームリソグラフィ）

6724002
An electron beam lithography system includes a laser for generating a laser beam, and a beam splitter for splitting the laser beam into a plurality of light beams.

熱酸化

熱酸化
thermal oxidation

4666556
IBM
By subjecting to thermal oxidation, the polysilicon is completely converted into a conformal (poly) silicon oxide layer having a thickness about 2.5 times that of the polysilicon layer.

シリコン窒化膜

シリコン窒化膜
silicon nitride film

4104090
IBM
A silicon nitride film is formed on the bottom of the monocrystalline silicon 1 and conventional masking photolithography techniques are used to form porous silicon regions 5'.

窒化膜

窒化膜
nitride film

6203613
IBM
For example to form a nitride film, it is necessary to introduce a nitriding reagent such as ammonia into the gas stream.

酸化物

酸化物
oxide

4352236
Intel
An oxide is grown on the substrate at predetermined first regions in the first area, forming first oxide regions and simultaneously an oxide is grown at predetermined second regions in the second area, forming second oxide regions.

窒化物

窒化物
nitride

6362109
A multi-step process is possible in which the different oxide and nitride levels are sequentially etched.

ハーフトーン型シフトマスク

ハーフトーン型シフトマスク
half-tone phase-shift mask

6338921
IBM
For example, U.S. Pat. No. 5,827,623 discloses a half-tone phase-shift mask designed to compensate for proximity effects.

斜入射照明

斜入射照明
oblique illumination

5840448
Intel
For exposure tools that use conventional or oblique illumination, better resolution can be achieved by lowering the wavelength of the exposing radiation or by increasing the numerical aperture of the exposure tool, but the smaller resolution gained by increasing the numerical aperture is typically at the expense of a decrease in the depth of focus for minimally resolved features.

パターン解像度

パターン解像度
pattern resolution

5972571
IBM
In fact, the present invention is suitable for manufacturing electronic components having pattern resolution on the order of about 0.175 microns.

コンタクトプラグ

コンタクトプラグ
contact plug

6750156
In electronic circuit fabrication, an interconnect feature, such as a wiring line or a contact plug, is used to electrically connect electronic features that are formed on a substrate.

酸化膜

酸化膜
oxide film

6368931
Intel
After first nitride film 26 is formed, an oxide film 28 may be formed in recess 18 upon first nitride film 26. Oxide film 28 may be formed by a dry dichloroethane (DCE) assisted oxidation with thermal oxidation.

層間絶縁膜

層間絶縁膜
interlayer dielectric film

6057250
IBM
In the manufacture of semiconductor electronic components, it is necessary to encapsulate the component in a glass or to use a glass as an interlayer dielectric film.

シンニング

シンニング
thinning

6677239
Silicon nitride loss may take the form of excess removal of silicon nitride, or "thinning" of the silicon nitride layer, from the desired amount 60 of silicon nitride.

エロージョン

エロージョン
erosion

6656842
As used throughout this disclosure, the term, "erosion" denotes the height differential between the oxide in the open field and the height of the oxide within the dense array.

ディッシング

ディッシング
dishing

6656842
As also used throughout this disclosure, the term "dishing" denotes a difference in height between the oxide and Cu within the dense array.

スラリ

スラリ
slurry

6280299
A slurry is delivered to the center of the polishing pad to chemically passivate or oxidize the film being polished and abrasively remove or polish off the surface of the film.

エアロゾル洗浄

エアロゾル洗浄
aerosol cleaning

5372652
IBM
An aerosol cleaning apparatus for cleaning a substrate includes an aerosol producing means having a nozzle head.

熱拡散

熱拡散
thermal diffusion

4209349
IBM
The next step is to diffuse a dopant through the mask opening 18 by either the thermal diffusion method or the ion implantation method.

ATE

ATE
automatic test equipment（自動検査装置）

6333706
IBM
However, when the chip 10 is connected to automatic test equipment (ATE), and is configured to receive a signal at the test in terminal 18, then the switches are actuated, as represented by a dashed line 26.

ヘトロエピタキシ

ヘトロエピタキシ
heteroepitaxy

6813409
IBM
In addition, mature Si processing technology, micromachining techniques, Silicon-on-Insulator (SOI) and heteroepitaxy, can be used to fabricate complex optical structures such as micro-optical devices and hybrid optoelectronics.

結晶方位

結晶方位
crystal orientation

6991999
The method of forming an electrode comprising: forming a lower polysilicon film having a crystal orientation dominated by the <111> direction;

格子定数

格子定数
lattice constant

6770134
The lattice constant of Ge is 4% larger than that of Si.

homoepitaxy

homoepitaxy
ホモエピタキシ

4728626
IBM
Thus, the 3D structure of FIG. 1 can be either homoepitaxy or heteroepitaxy in nature.

LPE

LPE
liquid phase epitaxy（液相エピタキシ）

4389768
IBM
Alternatively, the lightly doped semiconductor layer 30 may also be formed by known liquid phase epitaxy (LPE) or metal organic vapor phase epitaxy (MOVPE) or ion implanation techniques.

ALE

ALE
atomic layer epitaxy（原子層エピタキシ）

7078302
Dielectric layer 20 may be deposited to substrate 10 by a variety of deposition processes, such as rapid thermal oxidation (RTO), chemical vapor deposition (CVD), plasma enhanced-CVD (PE-CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), atomic layer epitaxy (ALE) or combinations thereof.

イオンプレーティング

イオンプレーティング
ion plating

6277253
Ion plating and CVD may be considered vacuum processes because they are generally carried out in a vacuum chamber.

ECR

ECR
electron cyclotron resonance

6518206
The source of the high density plasma may be any suitable high density source, such as electron cyclotron resonance (ECR), helicon resonance or inductively coupled plasma (ICP)-type sources.

ICP

ICP
inductively coupled plasma

6444408
IBM
Suitable plasma tools include electron cyclotron resonance (ECR), helicon, inductively coupled plasma (ICP) and transmission-coupled plasma (TCP) systems.

スカベンジャー

スカベンジャー
scavenger

6455232
In accordance with the invention, the scavenger reacts with the free fluorine generated by the dissociation of fluorine-containing polymer during the resist strip step and reduces the content of free fluorine in the plasma.

PEB

PEB
post-exposure bake

7141692
IBM
This "post-exposure bake" (PEB) process is carried out at a temperature below the T.sub.g of the silsesquioxane, which, as noted elsewhere herein, is greater than 50.degree.

TMAH

TMAH
tetramethyl ammonium hydroxide
（水酸化テトラメチルアンモニウム）

半導体の製造工程において使用される現像液のひとつを指す。

6605394
This developer is a 2.38 wt % solution of tetramethyl ammonium hydroxide (TMAH).

RET

RET
Resolution Enhancement Techniques（超解像技術）

6268093
Another method for increasing the resolution of the image is the use of RET (Resolution Enhancement Techniques) which include: off axis illumination, OPC (Optical Proximity Correction) reticles, and PSM (Phase Shift Mask) reticles.